The present invention relates to an asynchronous transfer mode (ATM) transmission apparatus, an ATM exchange, and an ATM multiplexer.
In FIG. 10, a switch system includes, for each of the output high ways 125-1 to 125-L, as many buffers as there are input high ways 120-1 to 120-K. Each input highway transfers an ATM cell (to be simply called a cell herebelow) conforming to the CCITT Recommendation I.361. The cell has a header field containing a virtual path identifier (VPI).
The cell is assigned with an input highway number in an input port. At an entrance of each switch, an address filter (AF 121-1 to AF 121-K) checks the VPI assigned to a received cell and an input highway number thereof to decide whether or not the cell is delivered to an output highway associated with the address filter. Passing through the address filter, the cell enters a buffer (122-1 to 122-K) to await an output timing. A selector 123 is used to select either one of the outputs from the buffers so as to output a selected cell to an output highway. The configuration of FIG. 10 further comprises a buffer control circuit 124 and concentration space-division switches 126-1 to 126-L.
Alternatively, in the input port, the pertinent cell is assigned with an output highway number for an output thereof. At an entrance of each switch, the address filter checks the output highway number assigned to a received cell to determine whether or not the cell is delivered to an output highway to which the address filter belongs. The cell having passed the address filter is loaded in a buffer associated therewith to wait for an output timing. The selector 123 then selects either one of the outputs from the buffers so as to output a selected cell to an output highway, thereby accomplishing a cell switching operation.
An example related to the present invention has been described, for example, the JP-A-2-161851.
In the conventional technology, in order to lower the cell loss probability according to the switching method in which buffers are disposed for the respective output highways, each buffer is required to have a large capacity. Consequently, it is difficult to form, in a large-scale integrated (LSI) chip, the plural buffers 122-1 to 122-K and the buffer controllers 124 related thereto as shown in FIG. 10. To overcome this difficulty, it is necessary in an actual switch system to dispose a plurality of buffer LSI chips and separated control LSI chips controlling the buffers. This accordingly increases the number of LSI chip kinds to be developed. Moreover, although a large-capacity buffer is needed to configure a switch having a low cell loss probability, the buffer size is also restricted by the capacity of the LSI chip. This has heretofore made it difficult to implement a switch developing a low cell loss probability.